The present invention relates to a semiconductor device and a process for fabrication thereof. More particularly, the present invention relates to a semiconductor device having a capacitive element of MIMC structure and a process for fabrication thereof.
There are two types of conventional capacitive elements formed on the semiconductor substrate (such as silicon substrate). One is of MIS capacitor structure which is characterized in that a low-resistance diffused layer formed in the semiconductor substrate functions as the lower electrode layer. Another is of MIMC structure which is characterized in that a conductive layer formed on an insulating film on the semiconductor substrate functions as the lower electrode layer. Conventional capacitive elements of MIS capacitor structure and MIMC structure are briefly explained in the following with reference to FIG. 11 and FIG. 12, respectively.
A conventional capacitive element of MIS capacitor structure is shown in FIG. 11. It has a p-type semiconductor substrate 60, a field oxide film 62 on the surface of the substrate, and an element region isolated by a p+-type element isolating region 64 under the field oxide film. In the element region is an n-type impurity diffused layer 66 which functions as the lower electrode. On the n-type impurity diffused layer 66 (which functions as the lower electrode) is formed a first upper wiring layer 70a (which functions as the upper electrode), with a SiN dielectric layer 68 interposed between them. A second upper wiring layer 70b is formed which is connected to the n-type impurity diffused layer 66 (which functions as the lower electrode) through a via hole made in an interlayer insulating film 72 and the SiN dielectric layer 68. Thus, the capacitive element 74 of MIS capacitor structure is constructed such that the SiN dielectric layer 68 is held between the n-type impurity diffused layer 66 (which functions as the lower electrode) and the first upper wiring layer 70a (which functions as the upper electrode). There exists a parasitic capacity between the capacitive element 74 of MIS capacitor structure and the p-type semiconductor substrate 60. This parasitic capacity is dominated by the PN junction capacity between the n-type impurity diffused layer 66 (which functions as the lower electrode) and the p-type semiconductor substrate 60.
A conventional capacitive element of MIMC structure is shown in FIG. 12. It has a p-type semiconductor substrate 60 and a lower wiring layer 78 (which functions as the lower electrode), with an insulating film 76 interposed between them. On the lower wiring layer 78 (which functions as the lower electrode) is formed a first upper wiring layer 82a, with a SiN dielectric layer 80 interposed between them. A second upper wiring layer 82b is formed which is connected to the lower wiring layer 78 (which functions as the lower electrode) through a via hole made in an interlayer insulating film 84.
Thus, the capacitive element 86 of MIMC structure is constructed such that the SiN dielectric layer 80 is held between the lower wiring layer 78 (which functions as the lower electrode) and the first upper wiring layer 82a (which functions as the upper electrode). There exists a parasitic capacity between the capacitive element 86 of MIMC structure and the p-type semiconductor substrate 60. This parasitic capacity is dominated by the capacity between the lower wiring layer 78 (which functions as the lower electrode) and the p-type semiconductor substrate 60.
On account of their construction mentioned above, there is a difference in parasitic capacity between the conventional capacitive element 74 of MIS capacitor structure and the conventional capacitive element 86 of MIMC structure. Usually, the latter permits its parasitic capacity to be reduced more easily than the former, because the insulating film 76 is thick. In addition, the latter is particularly suitable for high-frequency applications. Therefore, the capacitive element of MIMC structure is usually employed if it is necessary for the capacitive element to have a high capacity, a low parasitic capacity, and a low parasitic resistance.
Although the conventional capacitive element of MIMC structure has a smaller parasitic capacity as compared with that of MIS capacitor structure, it cannot be freed of its parasitic capacity completely because there exists a semiconductor substrate under the capacitive element, with an insulating film interposed between them. In order to realize a high-performance capacitive element with a low parasitic capacity, it is necessary to reduce further the parasitic capacity of the capacitive element of MIMC structure.
One way to meet this requirement is to employ an SOI (Silicon On Insulator) substrate having an insulating film. The use of this substrate greatly helps to reduce parasitic capacity. Unfortunately, this substrate suffers the disadvantage of complicating the steps for fabrication of integrated circuits, which is economically unjustifiable.
There is another way of reducing parasitic capacity by making thicker the interlayer insulating film between the semiconductor substrate and the capacitive element of MIMC structure. The disadvantage of this way is a necessity to form a deeply stepped electrode for connection of wires in multi-layer structure. Connection in this manner tends to cause incomplete contact.